The present invention generally relates to a method of depositing on a substrate an amorphous silicon based film that has controlled electrical conductivity and more particularly, relates to a method of depositing an amorphous silicon based film that has controlled conductivity in between that of an intrinsic amorphous silicon and an n+ doped amorphous silicon. The film may be deposited onto a substrate by a chemical vapor deposition process.
In recent years, flat panel display devices have been developed for use in many electronic applications including notebook computers. One such device, an active matrix liquid crystal display, has been used frequently. However, the liquid crystal display device has inherent limitations that render it unsuitable for many applications. For instance, liquid crystal displays have fabrication limitations such as a slow deposition process of amorphous silicon on glass, high manufacturing complexity and low yield. The displays require a power-hungry fluorescent backlight while most of the light is wasted. A liquid crystal display image is also difficult to see in bright sunlight or at extreme viewing angles which present a major concern in many applications.
A more recently developed device of a field emission display (FED) overcomes some of these limitations and provides significant benefits over the liquid crystal display devices. For instance, the FEDs have higher contrast ratio, larger viewing angle, higher maximum brightness, lower power consumption and a wider operating temperature range when compared to a typical thin film transistor liquid crystal display device.
Unlike the liquid crystal displays, field emission displays (FEDs) produce their own light using colored phosphors. The FEDs do not require complicated, power-consuming backlights and filters and almost all the light generated by an FED is visible to the user. The FEDs do not require large arrays of thin-film transistors. A major source of yield problems for active matrix liquid crystal displays is therefore eliminated.
In a FED, electrons are emitted from a cathode and impinge on phosphors on the back of a transparent face plate to produce an image. It is known that such a cathodoluminescent process is one of the most efficient ways for generating light. Unlike a conventional CRT, each pixel in an FED has its own electron source, typically an array of emitting microtips. The voltage difference between the cathode and the gate extracts electrons from the cathode and accelerates them towards the phosphors. The emission current and thus the display brightness, is strongly dependent on the work function of the emitting material. The cleanliness and uniformity of the emitter source material are therefore essential.
Most FEDs are evacuated to low pressures, i.e., 10xe2x88x927 torr, to provide a long mean free path for emitted electrons and to prevent contamination and deterioration of the tips. Display resolution is improved by using a focus grid to collimate the electrons drawn from the microtips.
The first field emission cathodes developed for a display device used a metal microtip emitter of molybdenum. In such a device, a silicon wafer is first oxidized to produce a thick SiO2 layer and then a metallic gate layer is deposited on top of the oxide. The gate layer is then patterned to form gate holes. Etching the SiO2 underneath the holes undercuts the gate and creates a well. Molybdenum is deposited at normal incidence and, at the same time, a sacrificial material such as Ni is deposited from a source placed at the side of the device such that cones with sharp points grow inside the cavities. Emitter cones are left when the sacrificial layer is removed.
In another FED device, silicon microtip emitters are produced by thermally oxidizing a silicon substrate, patterning the silicon oxide to expose the underlying silicon substrate, and selectively etching the exposed silicon to form silicon tips. Further oxidation and etching protects the silicon and sharpens the points of the silicon tips.
In an alternative design, the microtips are added onto a substrate of desired materials such as glass, which is an ideal substrate material for large area flat panel display. The microtips can be made of conducting materials such as metals or doped semiconductors. In such a FED device, an interlayer with controlled conductivity between the cathode and the microtips is highly desirable. Proper engineering of the resistivity of the interlayer enables the device to operate in a stable and controllable fashion. The resistivity of the interlayer is in the order between an insulator and a conductor, while the actual desired value depends on the specifics of the device design.
Chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) are processes widely used in the manufacture of semiconductor devices for depositing layers of materials on various substrates. In a conventional PECVD process, a substrate is placed in a vacuum deposition chamber equipped with a pair of parallel plate electrodes. The substrate is generally mounted on a susceptor which is also the lower electrode. A reactant gas flows into the deposition chamber through a gas inlet manifold which also serves as the upper electrode. A radio frequency (RF) voltage is applied between the two electrodes which generates an RF power sufficient to cause a plasma to be formed in the reactant gas. The plasma causes the reactant gas to decompose and deposit a layer of the desired material on the surface of the substrate body. Additional layers of other electronic materials can be deposited on the first layer by flowing into the deposition chamber a reactant gas containing the material of the additional layer to be deposited. Each reactant gas is subjected to a plasma which results in the deposition of a layer of the desired material.
In the fabrication of a field emission display device, it is desirable to deposit an amorphous silicon based film that has electrical conductivity in an intermediate range between that of intrinsic amorphous silicon and n+ doped amorphous silicon. The conductivity of the n+ doped amorphous silicon is controlled by adjusting the amount of phosphorus atoms contained in the film. Even though it is possible, in principle, to produce an intermediate conductivity film by adding very small amounts of phosphorus atoms, it is a very difficult task, i.e. requires specially premixed PH3/H2 to precisely control the amounts of the phosphorus atoms.
Since field emitting display devices use very thick layers, it becomes necessary to deposit low stress films to prevent warping of the glass and peeling of the films. The standard process for depositing amorphous silicon produces films that are highly compressive, especially when deposited at high deposition rates.
The present invention provides a deposition method for preparing amorphous silicon based films with controlled resistivity and low stress. Such films can be used as the interlayer in the FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition method described in the present invention employs the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used.
In one aspect, the invention features a method of forming an amorphous silicon-based film on a substrate located inside a deposition chamber, comprising: introducing a silicon-based volatile into the deposition chamber; introducing into the deposition chamber a conductivity-increasing volatile comprising one or more components for increasing the conductivity of the amorphous silicon-based film; and introducing into the deposition chamber a conductivity-decreasing volatile comprising one or more components for decreasing the conductivity of the amorphous silicon-based film.
In another aspect, the invention features a method of forming an amorphous silicon-based film on a substrate located inside a deposition chamber, comprising: introducing a silicon-based volatile into the deposition chamber; introducing phosphine into the deposition chamber; and introducing a nitrogen-containing volatile into the deposition chamber.
In yet another aspect, the invention features a method of forming an amorphous silicon-based film on a substrate located inside a deposition chamber, comprising: introducing a silicon-based volatile into the deposition chamber; introducing phosphine into the deposition chamber; and introducing a carbon-containing volatile into the deposition chamber.
Embodiments may include one or more of the following features.
The conductivity-increasing volatile and the conductivity-decreasing volatile may be introduced into the deposition at respective relative flow rates selected to achieve a desired film resistivity. The relative flow rates may be selected to achieve a film resistivity of about 103-107 ohm-cm. The conductivity-increasing volatile may consist of phosphine and the conductivity-decreasing volatile may consist of ammonia, the phosphine and the ammonia being introduced into the deposition chamber at a flow rate ratio in a range of about 1:1000 to about 1:10 (phosphine:ammonia). Alternatively, the conductivity-increasing volatile may consist of phosphine and the conductivity-decreasing volatile may consist of methane, the phosphine and the methane being introduced into the deposition chamber at a flow rate ratio in a range of about 1:100 to about 1:1 (phosphine:methane).
The conductivity-increasing volatile may comprise a dopant. The dopant may comprise an n-type dopant (e.g., phosphorous) or a p-type dopant (e.g., boron).
The amorphous silicon-based film may be characterized by a band gap, and the conductivity-decreasing volatile preferably comprises a band gap increasing component that increases the band gap of the amorphous silicon-based film relative to a film formed under similar conditions but without the band gap increasing component. The conductivity-decreasing volatile may comprises nitrogen, ammonia, N2, N2O, carbon (e.g., methane).
In one embodiment, the silicon-based film consists of silane, the conductivity-increasing volatile consists of phosphine, and the conductivity-decreasing volatile consists of ammonia. In another embodiment, the silicon-based film consists of silane, the conductivity-increasing volatile consists of phosphine, and the conductivity-decreasing volatile consists of methane. In yet another embodiment, the silicon-based film consists of silane, the conductivity-increasing volatile consists of phosphine, the first conductivity-decreasing volatile consists of ammonia, and the second conductivity-decreasing volatile consists of methane.
A second conductivity-decreasing volatile may be introduced into the deposition chamber.
In a preferred embodiment, amorphous silicon based films of precisely controlled electrical conductivity and low stress are produced by flowing a reactant gas mixture into a plasma-enhanced chemical vapor deposition chamber. The reactant gas mixture comprises silane, ammonia and phosphine carried by a hydrogen gas. Changing the phosphorus content by controlling the phosphine partial pressure, the n-type electrical conductivity of the amorphous silicon based film can be changed, i.e. increasing the phosphorus content increases the electrical conductivity. Changing the nitrogen content of the reactant gas by controlling the ammonia partial pressure, the resistivity can be changed, i.e. increasing the nitrogen content increases the resistivity of the amorphous silicon based film. An ideal range of resistivity for the field emission display devices is between about 103 and about 107 ohm-cm. The novel method described in this invention enables one to control the resistivity of an amorphous silicon based film within the desirable range of 103 to 107 ohm-cm. The films produced by the novel method have low tensile stress such that warping or peeling of films from substrates are avoided.
The present invention is also directed to a field emission display device fabricated by a plasma-enhanced chemical vapor deposition technique in which a reactant gas mixture comprising silane, hydrogen, phosphine (carried in hydrogen) and ammonia is used to produce an amorphous silicon based film having controlled electrical conductivity. By adjusting the flow rate of each component gas, an amorphous silicon based film having a precisely controlled electrical conductivity and low stress for forming a field emission device can be obtained.
Among the advantages of the invention are the following.
The invention provides a method of depositing amorphous silicon based films that have controlled conductivity and low stress in a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process by incorporating simple process control steps. The invention also provides a method of depositing amorphous silicon based films that have controlled conductivity and low stress in a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process by using a reactant gas mixture containing PH3 and NH3. The present further provides a method of depositing amorphous silicon based films that have controlled conductivity and low stress in a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process by controlling the flow rates of the reactant gases in the reaction chamber.
Other features and advantages will become apparent from the following description, including the drawings and the claims.